Saleae Logic2 Analog filtering technical details?

I am trying to understand the technical limitations of Saleae Logic’s analog inputs. I am aware of the support articles:

“In addition to the hardware AA filter, there is a digital-analog filter that engages for sample rates lower than the advertised sample rate. This is called the decimation filter. It will filter the data further before down sampling so data sampled at lower rates does not suffer from aliasing from frequency components that made it through the analog AA filter.”

“To accurately record an analog signal, you must sample at least 10 times faster than that signal. That is due to the filter response of our down-sampling filter as well as the hardware anti-aliasing filter that defines the maximum analog bandwidth of the device.”

… however, I was surprised at the apparent ‘extra filtering’ (in a software guys opinion) coming through on what I thought were ‘sufficiently extra’ sample frequencies when studying I2C signals. See picture below – plotting the SCL analog voltage sampled at different frequencies (50 MS/s, 6.25 MS/s, and 3.125 MS/s) as well as the ‘digital’ signal (@500 MS/s).

Note: these are all for an I2C SCL frequency of 400 kHz

So, the questions are:

  1. What are the electrical characteristics of the HARDWARE filter on analog channels? Per datasheet, claim 5 MHz bandwidth on 50 MS/s data, so I assume a low-pass RC filter? Can you share the R & C values / details on this?

  2. What exactly is the software ‘decimation filter’ implemented when selecting other analog sample frequencies besides 50 MS/s? Also, is this filtering implemented within the FPGA (ahead of USB data stream) or on the PC side (after USB received to Logic2 software)?

  3. Any chance we could (optionally) turn OFF the software ‘decimation filter’ and just do an ‘unfiltered decimation’ simple down sampling instead? Yeah, I know that Nyquist sampling theorists will scream about risks of aliasing – but you can only alias signal that actually exists on the input.

If we have our own hardware filtering (R’s and C’s), then we (hopefully) shouldn’t need any extra software filtering – and I’d like to have less ‘rounded’ and ‘attenuated’ analog waveform that is >10X my underlying operating frequency. Unfortunately, these digital clocks are not sinusoidal, they are square waves – so the software filtering can lose the sharp edges and signal peaks & valleys that I’d still like to see.

A quick follow-up:

I found a YouTube video that discusses more about the aliasing topic.
… it seems like the minimum sample rate for 400 kHz SCL should be:
3 x 2.5 x 400 kHz == 3 MHz

However, neither the 3.125 MS/s nor the 6.25 MS/s settings appear to capture the ‘complex’ (square) waveform, but rather it seems to be filtered down to a more sinusoidal wave (as though I’m being bandwidth limited by the decimation filter built in to Saleae’s analog signal chain?)

Finally, here’s a clip discussing more about bandwidth limitations affecting the captured waveform:

In this example – just changing scope’s bandwidth setting from 1 MHz to 5 MHz seemed to ‘square up’ the 1 MHz square wave (5X bandwidth) better than I could capture on the Saleae Logic with a sample rate setting over 15X vs. fundamental frequency (i.e., the 6.25 MS/s vs. 400 kHz SCL frequency still looks way more sinusoidal than the YouTube example).

Note: I realize I’m mixing the bandwidth vs. sample rate settings and the two are different, but I’m providing an example of the waveform capture behavior that I’m hoping to achieve.

The higher level point I’m trying to make, is that I believe the underlying analog data I want captured is technically available inside the Saleae hardware, so I’m looking for an option to see it rather than it being ‘lost’ in the analog signal chain. Maybe the decimation filter is bandwidth limiting more than the minimum required to provide the maximum visibility of higher frequency content?

For reference – here are some screenshots from the original Saleae Logic captures:

50 MS/s - clean picture (but 125X the SCL frequency):

6.25 MS/s - sinusoidal (but >15X the SCL frequency):

3.125 MS/s - sinusoidal and attenuated (even though ~8X the SCL frequency):

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@BitBob Besides sampling at the maximum advertised sampling rate for your device, we unfortunately don’t have a way of turning off the decimation filter manually.

You bring up some great points, and thanks so much for sharing a plot of the analog samples over time. It does seem to become ‘rounded’ when sampling at our recommended minimum sampling rate value of 10x the frequency of the signal.

I’ll need to pull together some of our team members to get their thoughts on the points you brought up and we’ll get back to you on this.

Hi @timreyes, FYI –

I did another few experiments with a signal generator, with a ‘square wave’ output set to 2.5V peak-to-peak and 1.25V Offset and created an Excel chart with the combined CSV data exported (and zoomed in) from two separate captures:
Trial #1 (T01):
Saleae Logic Pro @50 MS/s analog
PicoScope @ ~3MS/s

Trial #2 (T02):
Saleae Logic Pro @3.125 MS/s analog
PicoScope @ ~3MS/s

Notice that the PicoScope analog data is apparently NOT as filtered even using a lower sample rate (i.e., ~3 MS/s vs. 3.125 MS/s).

I also noticed that the PicoScope 6 software has some sampling options, such as:

  • Sin(x)/x Interpolation (I had this turned OFF in “Tools > Preference > Sampling”)
  • Bandwidth Limit set to “None” (could have set to “20 MHz”) on the channel

I wasn’t sure if Saleae Logic2 software (or the FPGA firmware) is doing one (or both) of these settings (interpolation and/or bandwidth limiting) automatically, and without user-configurable method to turn the feature(s) OFF?

E.g., had the software/firmware done a simple sample decimation, then I expect the results would have been pretty similar to the PicoScope – the waveform would have been more ‘square’ than ‘sinusoidal’ and would NOT have been attenuated either.

I look forward to better understanding the analog signal chain design – as I use my Saleae Logic Pro more for its digital features, but it would be nice to more fully exploit the analog capabilities, too (without unnecessarily wasting memory @50 MS/s).

[Edit: update]

I did some additional analysis with the waveform generator and the Saleae Logic2 software ‘Measurement’ tool, and found some data to indicate that the decimation filter frequency response may be below 400 kHz for the 3.125 MS/s analog sample rate?

E.g., given waveforms w/ 2.5Vpp and +1.25V offset:

[Correction] 1.25V * SQRT(2)/2 + 1.25V = ~2.13V (~3 dB point)
[was: 2.5V * SQRT(2)/2 = ~1.77V – but 2.5V isn’t the right signal magnitude]

Set analog capture to 3.125 MS/s sample rate

400 kHz Square:
Vpp 1.5977706909179688 V
Vmin 0.45788028836250305 V
Vmax 2.0556509494781494 V (~0.64 gain)
Vavg 1.2542787790298462 V
Q5% 0.47309714555740356 V
Q95% 2.0404341220855713 V

490 kHz Square:
Vpp 1.0296744108200073 V
Vmin 0.7419284582138062 V
Vmax 1.7716028690338135 V (~0.42 gain)
Vavg 1.2574741840362549 V
Q5% 0.7520729899406433 V
Q95% 1.7614582777023315 V

490 kHz Sine:
Vpp 0.8064938187599182 V
Vmin 0.8535187840461731 V
Vmax 1.6600126028060913 V (~0.33 gain)
Vavg 1.2538232803344727 V
Q5% 0.8585910797119141 V
Q95% 1.6508824586868285 V

444 kHz Sine:
Vpp 1.0347466468811035 V
Vmin 0.7368561625480652 V
Vmax 1.7716028690338135 V (~0.42 gain)
Vavg 1.2547069787979126 V
Q5% 0.7470007538795471 V
Q95% 1.7614582777023315 V

Am I missing something, or analyzing this wrong … ?

[Edit: - added +1 waveform measurements, and updated gain calculations above]

297 kHz Sine:
Vpp 1.7499394416809082 V
Vmin 0.3817959427833557 V
Vmax 2.131735324859619 V (~0.71 gain)
Vavg 1.2577297687530518 V
Q5% 0.3970127999782562 V
Q95% 2.1215908527374268 V

Finally, an external reference for more about ‘decimation’ and ‘downsampling’ :

@BitBob Thanks for all of the added info! I’ll add your additional notes to our backlog.