Note: The Saleae employees can and most likely will give you a more complete answer.
When I have done something similar to this, most recent reading results from a camera, which sends 8 bits of data… I used the Simple Parallel analyzer
The issue is that for this I typically need to setup 8 Data pins D0-D7 AND a clock pin … Which does not fit on my newer faster Logic Pro 8… So I use my older Logic 16. And in my case I also wish to see a few more signals like HSYNC and VSYNC…
Not sure if there is any way for this analyzer or another one to not use a clock signal but instead try to guess or specify a logical clock.
Again hopefully someone there can give you a better answer.
The issue with a clock signal is knowing when is the appropriate time to sample the 8 signals to get the data. Typically it is with another signal (clock) where you configure which signal is clock and if you should sample when the clock signal is going high or when it is going low.
Without this, you would probably need some form of user input, like maybe like set a Marker on one place to do a sample and either set a second one to give you the speed to do it.
Alternatively it would be interesting to see how good maybe the analyzer could guess.
That is in your example photo, maybe look for sets of pulses and take a set of samples of the different widths of highs and lows, and see if there appears to be a common size for the smaller ones. Which may give you a clue of the pulse width. Now see how well it works if you set the sample point at the center of one of these and see how good of results you get…
Maybe they already have something like this and/or it might be a good feature request, as there are probably many of us who have Logic 8s and/or Pro Logic 8s and would like to clock in 8 bit signals like this… Or have Logic 16s and wish to clock in 16 bits.
Imagine you have a system stepping through addresses in the ROM and the data for a span of several hundred, or several thousand, bytes is the same. How can the analyzer know that a new data value is being presented without a clock signal of some sort that matches address changes?
If the process you are watching repeats you could collect the data in two passes by capturing four bits at a time instead of eight and use one of the other lines as a clock source.
If you don’t have a suitable clock then the problem becomes much harder. If you describe in more detail what you are trying to achieve we may be able to make better suggestions.
I am not an expert, but if the line is changing from Low to Hi then you can see the individual bits coming even without a clock. If there is a single High-to-Low or Low-to-High it means the state is changing and we are tracking exactly this change.
Once you see a change on one channel then you can look the states of the other channels at this very moment and you can reconstruct a value. The idea is to use one of the channels (that changed) as a clock.
Maybe there could be a small delay while all the 8 channels change state, but it will be very small. Maybe it can be encoded as a very small time value parameter. So we select one channel that changed as reference and then we check the state of the others with small delay (to make sure we get the final state).
What do you think? I think it is doable, it is a question of coding it as analyzer.
writing an analyzer that decodes data using edges on the data lines to generate clock information is quite possible. Success depends a lot on the nature of the system you are working with. I’m sure you can imagine very common situations where the address changes but there are not changes in the data. In such a case the analyzer can’t sense new data.
A system could be designed that extracts a fixed rate clock from detected data edges. That only works if the ROM outputs update at a constant rate. Such a system can’t operate reliably in real time. At the very least the first few “clocks” are likely to be wrong. If the test system clock is unstable compared to the logic analyzer sample clock it can be very difficult to extract a reliable data clock.
Again, if you tell us more about the system and what you are trying to measure we may be able to help more. At present I can only point out problems because there are many situations where what you want can’t easily be achieved. Maybe you have a situation where it is easy?
I could not understand what you mean by “where the address changes”. What address?
I am trying to study if the ROM chip MK38036N outputs correctly its ROM. I have the first 8 bytes that the ROM chip will output if it working correctly and I want to compare with the readings I get from the logic analyzer.
The pins of MK38036N are described here. There are 8 data pins called Q0, Q1 … Q7. Sometimes they are named D0 … D7. There is no CLK pin. Still I think the CE pin goes LOW every time a byte is outputted on the D0-D7. So maybe it can be used as a clock. Still this means I will have one channel less and I won’t be able to reconstruct the values directly.
So you can adopt the approach I suggested above of using two captures to collect 4 bits at a time allowing one of the unused logic analyzer inputs to be used as a clock using the !CE line.
However if this is a one time thing it’s probably a whole lot quicker to eyeball the results for just 8 bytes of data.
Note that if this is data from an IBM-PC ROM measured in situ during boot up the bytes fetched are not the first 8 bytes stored in the ROM, but are the reset jump vector bytes and that will depend on the specific version of the BIOS.
So it seems that the /OE or /CE can be used for clock. Then I recorded 4 pins D7-D4. I set the detection on the rising edge of /OE. Then one needs to be careful in which order the bits are 1110 or 0111. I have to test more, but it seems that it is working.