There was a project for Logic V1 that provided basic functionality for decoding clockless parallel busses (GitHub - Zweikeks/saleae-logic-SimpleParallelNoClock-Analyzer: Plugin for Saleae Logic Software. Analyzer for parallel data communication without a clock signal. The data word transmitted is re-evaluated on every data transition.), I have updated it to work v2 here:
GitHub - ablaylock/SimpleParallelNoClock: Taken from Zweikeks/saleae-logic-SimpleParallelNoClock-Analyzer and updated to use new SDK
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