Parallel bus display


I often have to look at state machine and there is actually no convenient way of displaying them.
Bus display for digital logic analyzer without any clock is a basic feature which is lacking here.


@Bear Currently, we’re tracking an idea below for an analyzer that decodes simple digital data, without the reliance of a clock, nor the reliance of a specific data structure required by our Async Serial Analyzer (e.g. Start bits, stop bits, etc). Apologies this isn’t readily available right now.

If that kind of analyzer is something you need, feel free to add a comment to the idea post above as to how you’d prefer the analyzer to decode your data!

At the moment, users can use our protocol analyzer SDK to create an analyzer like this via C++. More information on our SDK can be found below:

Also, just in case I’m not misunderstanding any of your requirements, feel free to attach a sample .sal capture file with the data you’d like to decode, and a short explanation of how you’d like it to be decoded. I can double check if there are any existing analyzer that might be able to do the job.


I know about this ticket but there seems to be no progress.
I will check back in six month.

I understand that this is complicated by the way your SW is construct however it’s still a basic feature.


@Bear The idea for a simple bus analyzer is unfortunately not on our roadmap at the moment. With only 3 software developers on the team, we’re stretched quite thin and laser focused on some higher priority features and stability fixes right now. Feel free to check back in the future, but the best solution would be to utilize our protocol analyzer SDK if you need to build a custom solution immediately.


Any update ?
Thats good to see feature requested in
But no roadmap or plan is showed as summary.
It’s also difficult to track release note of the client.
Is there a way to be involved as volunteer in dev to make further progress.
I’m pretty sure the automation API will be off greet help and many people would develop it.


No update at this time. I wish we could get started on this right away, but the truth is that our roadmap is pretty packed to the middle of next year right now.

I really want to expand the python API to support creating new channels of any type (digital, analog, or protocol) from existing channels of any type. This would make this feature quite easy to add.

It can be done today with our C++ Analyzer SDK, however it’s a bit tricky, due to limitations of our API, which is designed to scan only one data channel at a time. That works great for clocked protocols, but it’s not ideal for asynchronous multi-channel signals like this.

Is there a way to be involved as volunteer in dev to make further progress.
Yes, you could fork the simple parallel analyzer, and convert it to not use a clock:
GitHub - saleae/simple-parallel-analyzer: Saleae Simple Parallel Analyzer

The core loop of the protocol analyzer revolves around advancing to the next clock edge:

Then there is a good amount of code after that that’s purely there to extract the last edge of the data. This is a common problem with the existing analyzer SDK, and something we would like to improve for the next release.

To build a generic parallel decoder, I would:

  1. remove the clock channel from the settings.
  2. optionally add a setting for the minimum state duration worth decoding. When an asynchronous parallel bus changes state, not all signals are guaranteed to transition on exactly the same sample, and if the parallel bus is being bit-banged one bit at a time, there could be quite a bit of skew between transitions. You could add a feature to filter out these short lived intermediate states.
  3. refactor the loop to use WouldAdvancingToAbsPositionCauseTransition on each channel, one channel at a time, some fixed amount. Alternatively, DoMoreTransitionsExistInCurrentData combined with AdvanceToNextEdge would be much for efficient, but slightly trickier to code. It will be a bit tricky to get right, since there is no convenience function “find next transition on a set of channels” but it’s not impossible.

There was a project for Logic V1 that provided basic functionality for decoding clockless parallel busses (GitHub - Zweikeks/saleae-logic-SimpleParallelNoClock-Analyzer: Plugin for Saleae Logic Software. Analyzer for parallel data communication without a clock signal. The data word transmitted is re-evaluated on every data transition.), I have updated it to work v2 here:
GitHub - ablaylock/SimpleParallelNoClock: Taken from Zweikeks/saleae-logic-SimpleParallelNoClock-Analyzer and updated to use new SDK


@allenb That’s fantastic, and thanks for sharing that! I’ve added your version of the parallel clockless analyzer below: