Parallel bus display


I often have to look at state machine and there is actually no convenient way of displaying them.
Bus display for digital logic analyzer without any clock is a basic feature which is lacking here.


@Bear Currently, we’re tracking an idea below for an analyzer that decodes simple digital data, without the reliance of a clock, nor the reliance of a specific data structure required by our Async Serial Analyzer (e.g. Start bits, stop bits, etc). Apologies this isn’t readily available right now.

If that kind of analyzer is something you need, feel free to add a comment to the idea post above as to how you’d prefer the analyzer to decode your data!

At the moment, users can use our protocol analyzer SDK to create an analyzer like this via C++. More information on our SDK can be found below:

Also, just in case I’m not misunderstanding any of your requirements, feel free to attach a sample .sal capture file with the data you’d like to decode, and a short explanation of how you’d like it to be decoded. I can double check if there are any existing analyzer that might be able to do the job.


I know about this ticket but there seems to be no progress.
I will check back in six month.

I understand that this is complicated by the way your SW is construct however it’s still a basic feature.


@Bear The idea for a simple bus analyzer is unfortunately not on our roadmap at the moment. With only 3 software developers on the team, we’re stretched quite thin and laser focused on some higher priority features and stability fixes right now. Feel free to check back in the future, but the best solution would be to utilize our protocol analyzer SDK if you need to build a custom solution immediately.