Does Logic 2 support the “reset the starting sample” or “re-run starting at timing marker” for Async Serial, like V1.2.18?
I have a one-wire communication that does hardware test before serial message. Also, each byte has single-bit ACK from the other device at the 2nd STOP bit position. I can work around 2nd STOP bit being detected as START bit, because I can re-run the starting based upon timer mark.
Also, your Asyc Serial model supports 12-bit frame, but it moves to satisfy the start and either 1st or 2nd stop bit!