Incorrect Reading of SPI signal

Hello, we are using the saleale logic 8 to read data transfer between an STM32 MCU and an IC through SPI.
The CLK frequency is 1.5 for the SPI configuration with a prescaler of 2 so at the end we have CLK of 750 kHz.
For some reason we can’t read the data properly through the MISO channel with this configuration, even though the saleale has a sample frequency of 50 Ms/s. The saleale configuration is correct and the MOSI signal is always read accordingly. The debugger always reads the correct values so the data being transfered is correct but the saleale reads it wrong. Find attached screenshots of the measurments.
Any idea of what could we be doing wrong?
should be reading 0xAA:

should be reading 0x02:

You have the SPI clock set for leading edge (CPHA=0) rather than trailing edge (CPHA=1).

In the analyzers’ panel click on the three vertical dots that show up to the right of the appropriate analyzer when you move the mouse over it. Click on the dots to get the popup menu. Click Edit to get the SPI settings dialog. The setting you want is “Clock Phase”.

The arrows on the clock edges tell which edge is active. For most (all?) protocols having the data edges line up with the clock edge suggests something is wrong.

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Yup, clock polarity (CPOL) and clock phase (CPHA) always trip up our team on every SPI project we’ve worked on.

Place a timing marker on a rising (or falling) edge of SCLK, then zoom in a bit to see what side of the clock the bit changes.

It these two configs don’t get things aligned, then look at the analog for SCLK and MISO/POCI, and make sure you are triggering the Saleae at the right levels. Your Saleae is seeing zeros as ones. Make sure your voltage swings cleanly rail to rail.

If the transitions are clean, then also make sure your Saleae is looking at the same voltage levels as your MCU. Supported Voltages - Saleae Support . You’ll need to match VDDIO on your board. Are there any level shifters between MCU and IC? Is so, what side are you probing.

Just a few thoughts CPHA.


Thank you for the reply, you are right, for some reason the configuration wasn’t reading properly the MISO (sdo) values. As per the level shifters, there are none and the reading is the same on either side.
What we are struggling with is the fact that MCU configuration is the same both for miso and mosi and IC configuration is the same, the saleale reads properly the mosi line yet it is reading 0 as 1 in the miso line, it might have something to do with the IC.
Thank you again.


Hmm, there was a response suggesting you check the Logic 2 config for CPOL, that’s what I was responding to. It seems to have gone.

Everything you are saying makes it sound like the unit under test is working, so this makes it look like Saleae configurations isn’t right. I see there’s a lovely primer Learn SPI - Serial Peripheral Interface - Saleae Support, look for the heading on Clock Polarity and Phase, but if CPOL or CPHA were an issue, we’d see the value shifted, you see 0x55, or [0x15,0x40]instead of 0xAA and 0x04 or 0x01 instead of 0x02. This is why I’m thinking hte Saleae is not seeing a low as a low soon enough. This might happen if hte Saleae was configured for 1.1V while the MCU and IC are operating at 3.3V or 5V.

I’d seriously look at the analog values as the set up time seems to be violated. How fast is the transition from a 1 to 0?

A schematic review might also help.

  • Are PICO and POCI symmetric?
    • SDI is okay and SDO fails, so is there an imbalance?
    • Pullups?
    • Noise?
  • Is there a second SPI device who is fighting on the bus?
    • Check all CS lines to all SPI devices. Again, if the MCU is reading okay, then the saleae should.

Good luck with the hunt.


I “fat finger” deleted my reply accidentally. I’ve contacted Saleae to see if the reply can be restored.


@P.Jaquiery Done! I was able to recover your reply.

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