The initial state of the clockline does not match the settings

MY Spi clock is 10mhz and sample rate is 50ms/s ,voltage 3.3+v,
while transferring the data using spi in saleae am observing “the initial state of the clockline does not match the settings”
am using saleae 1.2.40 version
could you please look in to this

Well, the first question is, of course, going to be “is it right?” That is, are you transmitting the SPI with a different mode than you told Logic you were? The various modes have different resting states for the clockline so maybe you set the wrong mode.

If you set the proper mode, I’ve still found that some microprocessors will leave the clockline in an ambiguous state until you start to transmit the first time. Then everything magically goes to the way it was supposed to be. That can mess up the first transmission but thereafter it should be OK. That’s not Logic’s fault, that’s the MCU being silly in that case.

Edit: Also, a screenshot is worth a thousand words. If you are still having trouble then post a picture of the output and people will probably be able to help better.

As requested am sending the screenshot and I have used mode3 i.e., clock polarity 1 and phase 1 for some spi frames we are able to see the correct data , some of them were not getting

first line is enable,
second line is clock,
third line is MOSI,
fourth line is MISO in screenshot

@6011857 I’ll jump in here, but it looks like there’s a bit-count offset somewhere, or perhaps the number of clock edges recorded does not match the number of bits expected, which is usually caused by glitches on the clock line as we describe below (Under the “Common Issues With Noise Around Clock Edges” section).

Feel free to attach your capture file here as well and I can take a closer look.

As a side question, is there a particular reason you are using the older Logic 1.x software? We no longer officially support that version. We’ve fixed several bugs and added new features since then in the newer Logic 2 software downloadable below.