- Saleae connected to SPI lines and Saleae’s SPI analyzer is setup such that the “data is valid on clock trailing edge”.
- The device being analyzed has the following behavior documented “The data is updated on the falling edge of the clock pin at the programmed symbol rate”.
Does the Saleae read the MISO/MOSI line at the exact instant it receives a clock signal or does the Saleae allow the MISO/MOSI line to settle before reading it?
@maxfc2 The MISO/MOSI line is read at the exact instant it receives the specified clock edge. There is no settling time programmed into our SPI analyzer.
@timreyes, thank you that’s very helpful.
My device updates its data line on the falling edge, so it sounds like I should setup Saleae’s SPI analyzer to read the data on the rising edge (“data is valid on the clock rising edge”) to allow time for the data line to settle after its updated.
@maxfc2 Glad that helped! Yes, in your case, you would want Logic to read on the rising edges if the MISO/MOSI lines are transitioning at the falling edges.