Please refer to the post below for a more comprehensive description.
I’m recording the PWM signal sent to a stepper motor controller.
In this implementation, PWM duty cycle remains stable at ~50% but frequency changes from 127 to 500 Hz. Channel 0 captures steps and Channel 1 the direction.
I would absolutely love to see this type of capability too. An analog-ish ‘psudo-waveform’ showing RC-servo angles over time, for example. Or PWM duty cycle corresponding to motor power, etc. etc. Super super useful.
There are other ideas on there. One of which I made. The general idea is that it’d be nice if one could take data from one or more existing channels and turn that into data for a generated channel. Most of us wanted to go the other way from what you want. As in, maybe take an analog signal and turn it into a digital signal with hysteresis. But, I think the general idea is still the same - take data from one place, transform it, place it in a new channel. So, my recommendation would be for Saleae to make a generic interface for data transforming that allows people to generate new channel data.
Thanks @rei_vilo for getting those idea posts up, and for linking this discussion.
@P.Jaquiery I agree. This is actually one of the more requested features since Logic 1.x. I’m sure that even getting basic math added in as a starting point would be very helpful. I added this discussion thread to those idea posts as well.
Hi @stefan, thanks for letting us know your need for this! For your comment below:
I would like to create a virtual CS channel with f.x. CS = Line1 AND Line2; Then use this virtual CS as input to a SPI analizer
In that example, are you looking to only see data from ADC1 and ADC2, while ignoring (and not decoding) data from ADC3? In addition, I’m assuming that you also need to look at any other combination of data as well.
I added a comment for you in the idea post we are tracking for this:
We have a couple workarounds I can share:
You can set the Enable line to “None” in the SPI analyzer settings. This means that all data on that bus will be decoded (and will ignore the CS/ Enable line state)
You can add multiple SPI analyzers to the same SPI data bus, with each analyzer pointing to a different channel (i.e. different CS) for the Enable line. This will allow you to decode based on the CS line for that analyzer, and you can hide analyzers for the ADCs that you are not interested in at the moment.
Ahhh, that’s a cool usage! I would never have thought to make a feature like that in software but seeing your description it all sounds very reasonable. Yeah, this is another good reason why being able to make virtual channels would be handy.
This is fantastic! Thanks so much for sharing your schematic! It conveys your idea perfectly, and is an extremely useful and creative use case. I’m also a big fan of the channel usage efficiency (3 channels vs 8 channels) using this method.
