I am trying to capture SPI transfers between a STM32L1 processor and a ADT7320 temperature sensor. The ADT7320 spec states that the MOSI transfer is leading edge triggered and MISO is trailing edge triggered. I see a “settings mismatch” error on the MOSI and MISO channels in Logic 2 when capturing data.
Is it possible to trigger each channel differently?
@kl7jdq Oh interesting. I’ve attached an example capture file that shows settings that might be applicable in your case.
SPI-example.sal (46.9 KB)
In summary, I ended up configuring 2 separate SPI analyzers. One for MOSI configured to sample on the CLK leading edge, and one for MISO configured to sample on the CLK trailing edge like in the image below.
Thanks! It worked.
