Problems with SPI analyzer

I have a device that has 3 slaves on a SPI bus, 2 flash chips and a TPM chip. I can tap on the flash chip pins, but the TPM chip’s pins are inaccessible. I would like to take the logical AND of the flash CS pins, and construct the TPM CS from that. I think I have few options:
A) Generate the AND signal in logic 2, which to my understanding is not yet supported. Is that still correct?
B) Generate the AND signal by scripting, which is not officially supported since would need to generate files in propietary .sal format.
C) Create custom SPI analyzer which can take multiple enable signals.

When taking a look at the SPI analyzer, I noticed that the code expects that the enable bit pin does not toggle during transfer, but in my case the enable pin toggles with clock frequency when active. Is this normal behaviour for a SPI master? (see image below, D3=CLK, D1=CS1 and D2=CS2)

I managed to solve the problem with CS toggling by changing the option to 3.3+ Volts. This also resulted more consistent capture for other pins. Should had read the specs more carefully since the threshold is then actually 1.65V, not 3.3V.

@juuso Glad to hear you got that resolved! Sorry for the initial trouble with that. That’s correct — the actual voltage threshold will be approximately half of the voltage setting you select.

More information on the various voltage setting behaviors can be found in the support article below.