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Logic 2.3.13 fixes a bug affecting sample rates when only digital channels or only analog channels are enabled
Quick note: with the crash/hang I mentioned in recent build, where trimming data, that was not always reproducible…
I ran into another hang today with older Logic16, using Simple Parallel.
The steps were sort of like:
a) Bring up LA with 14 pins connected, and run the Simple Parallel with data on pins 2-9 clock on 12. I get a sample data looks wrong as clock is running at 16mhz as is fastest LA setting, so don’t see offset of Pixclk from masterclk…
b) Turn off channels 0-1, 6-9 so down to 8 channels, allows me to set LA to 32mhz. Do new sample.
c) The older Simple parallel errors out triangle saying needs new sample… So I added new parallel with just 4 data pins and pixclk for clock and data shows up. Obviously not all of the data as I am only getting 4 out of 8 data bits. But at least I can verify that the clock edge looks good. for getting data.
d) I delete the other Simple Parallel analyzer. Appears like it goes away
e) I try to get new sample, click start, nothing appears to happen. Try a few more times still nothing, close out program, restart it, does not see any Logic Analyzer devices. Turn off power to analyzer and turn back on, still nothing. Unplug it, plug it back it in still not. Finally after a couple of attempts, unplug it, leave the power off (USB Hub has switch to enable/disable each port). Start up software, once it is up, then turn back on power and finally it talked. Although it lost all of my previous settings for channels and the like.
Again may not be completely reproducible. But thought I would mention it.
Thanks,
Sorry I know that this is a secondary question, but wondering it there is some form of Analyzer or HLA that maybe counts how many pulses happen within some other pulse…
That is in the case I am looking at with a trying to read in a camera image and I am trying to setup some custom settings for a region of the image to read in. So for example I wanting to know how many rows of data are returned per image, so would like to count:
How many pulses in the bottom row for each of the Red pulses second from bottom…
And likewise, if one zooms in you see that bottom orange area:
is a lot of pixels, and would like to know how many of the clock signals (third from bottom) happened in each of those pulses… Not sure if that makes sense.
But assuming I figure out right settings the first count should be 320 and second counts should be 480, such that if correct, I can simply output the returned data to an ILI9488 display.
Is it enough that the Clock Stats digital measurement extension counts rising and falling edges in a measurement selection? That is, you shift drag over the clock burst and the measurer reports the number of rising (or falling) edges which is the number of clock edges.
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Thanks, that will get me a long ways there.
It is a lot easier than trying to count 
Again thanks,
Wondering at times though if one could control how the count actually outputs… That is:
In this case I want to verify that the actual count is 1280 (640x2)
So not sure with value of 1.227 k
In this case it actually takes up more room to display the K stuff…
I think the integral count issue is on Saleae’s radar. At least, the topic of integral counts has been raised before.
In any case there are enough digits there for the precision you need so your count is short of what you expect. Even if Saleae have scaled the number so k = 1024 (which is just plain wrong and I doubt they have), the adjusted value is 1256 which is still too small.
@KurtE I’m running some tests over here and I’m not able to reproduce the hanging issue with the Simple Parallel analyzer. Seems like some sort of edge case that I can’t seem to trigger.
- are you able to reproduce it with demo data? i.e. when a logic device is not connected.
- how often is it reproducible?
We also might be able to look into your logs. Feel free to send over your Machine ID privately via the link below:
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Thanks, I only hit this fully the one time… I have seen a few similar things, but have mainly tried to avoid getting into the issue.
The main thing I run into is the older logic 16 is not fully fast enough to truly get the right clock counds and the like when I have all of the channels active (2 I2C pins, 8 data pins, MCLK, PIXCLK, HREF, VREF) and the clock is MCLK running at a fast clock rate (don’t remember if set to 12 or 24 mhz right now)… So that was why some of counts were off. When I reduced down to 8-9 pins caould get this one to sample at 32 mhz which was showing me the clocks correctly.
Will let you know if I can reproduce again.
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