I just wanted to give a heads up about what I am cooking:
As you may know there is an open source logic analyzer solution called sigrok and it also supports analyzers written in python.
They have implemented a similar cascaded analyzers approach to the HLA concept, so I think it adds itself that with some glue code they could be used in the Logic 2 as a HLA.
At the moment sigrok has 40 analyzers which works on the top of the I2C/SPI/UART. (The interesting analyzers count could be higher since there could be some decoders depending on these first level decoders).
So I have started to work on this wrapper, you can find my work here:
It involves a lot of ditching and the analyzis is not yet working at any level yet. I just managed to load a sigrok analyzer to Logic and got the settings exposed on the UI and I am quite happy about it now
In the case if anyone has hints, ideas about this let me know here or on the github issues.