MDIO analyser

Hi.
We using logic8 pro to debug MDIO inteface with RTL8367RB.


I see that when data is sourced by PHY, the analyser is sampling by falling edge.
I tried to find how MDIO implemented in CPUs.
For example ST provides this diagram:

On the other hand TI draw something like this:

My question is what documentation was used when MDIO analyser was developed?

The MDIO analyzer source is on github, and I found the following issue reported:

The Saleae support article for MDIO analyzer references Wikipedia, which refers to the IEEE 802.3 standard(s)?

As noted in the github issue, the MDIO analyzer decoding could be incorrect if an MDC falling edge comes too fast (before MDIO transitions). However, I think it should work fine as long as each MDIO transition always beats the MDC falling edge (i.e., running at slower MDC clock speeds and/or PHY w/ shorter MDIO data delays).

MDIO References:

Were you having decoding problems, or just curious about how the MDIO analyzer was designed? What is your MDC clock speed for PHY? What is the MDIO data delay for PHY (from MDC rising edge to MDIO transition)? Are the MDIO transitions happening after MDC falling edges?

Also, what digital sample rate and threshold levels are you using? Have you looked at the analog signals, too? In this case, using the max/full analog bandwidth of 50 MS/s is recommended to see any subtle signal characteristics. However, if your MDC clock is running too fast and/or MDIO data delay is just too long, you may need to wait until the known issue above is resolved by Saleae (or provide a pull request on github if you can fix it yourself :wink:).

Hello.
Thank you for the reply.
I think I got it, documentation specifies timing for sourcing MDIO, not for sampling (unlike I2C).
Our problem is that analyzer result differ from what hardware reads. Offse is 1 bit (i.e. 0x3000 and 0x6000). Our bigger problem, that we don’t know what is the right answer for RTL8367RB :grinning:
We have been controlling analog signals with separate oscilloscope, levels are OK (3.3V) and logic8pro configured accordingly.
We will try to slow down the bus.