Logic 2.3.11

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Logic 2.3.11 fixes a few bugs and improves the way adjacent bubbles appear


Bug fixes

  • Fixed zero padding for data table exports
  • Fixed drag selection in data table to keep selection while scrolling
  • Fixed Select All shortcut (Ctrl+A) to only select data table rows

Hi, could bubbles be right-aligned so “0x” (for hexadecimal values) drops of first when the value does not fit? Reading “7A” is better than reading “0x”.


Thanks for the feedback. I see what you mean.

Although we probably wouldn’t change the alignment, would an option to completely remove the “0x” work for you?

More suggestions…

  • Toggle analyzers.
    Add a toggle switch to enable/disable them, exactly like the one from Trigger View. Currently, I have to delete the analyzer and re-add it again when I need it.

  • Fix channel resizing.
    Open a blank Logic 2, add 2 SPI analyzers. If you try to vertically resize the MISO and MOSI channels, you’ll notice that it doesn’t allow to swallow the channel designation (the small names below “Channel X”, like ‘SPI - MOSI’ or ‘SPI - MISO’). This is more of a UI inconsistency that triggers PTSD even on people without it. Either remove this restriction and allow to hide these designations (my favorite, as someone who always works with Logic tiled to either the top or bottom of my screen since, so I could use the wasted space), or enforce this on the CLK and CS channels as well.

  • Fix the line state box font size
    After a capture with the SPI analyzer for example, if you hover the mouse over, say, the CLK line, it shows the duty cycle, frequency and width of a wave period in a box on the side of the channel view. When you resize the channel vertically to the smallest possible size, the box is compressed, but the text inside doesn’t adjust to it, overlapping with the channel size, and hiding the top and bottom of the info box.


If 0x is removed only at need to fit space constraints.


For Toggle Analyzers I see what you mean. If instead of a toggle when you went to the analyzers and had a list of your most recently used analyzer would that help? Also, I’m curious about your use case of having to enable and disable analyzers vs. using different tabs?

For channel resizing the reason for the height limitations being different between the CLK and MISO/MOSI is due to MISO/MOSI channels needing to display both the digital signal plus the bubble for the analyzer. For the clock you can resize it smaller since only the digital signal appears there with no other information. We could do what you said which was to force the minimum for both, but if you want to make things as small as possible it seems like an ok trade off?

I see what you mean for the instantaneous measurement box. I’ve added it to my list of UX improvements.

Thanks for your feedback!

If instead of a toggle when you went to the analyzers and had a list of your most recently used analyzer would that help?

No. Read on.

I’m curious about your use case of having to enable and disable analyzers vs. using different tabs?

By tab you mean session? Regardless, I use Logic to debug 2 SPI devices, therefore 2 analyzers. It’s not always that both peripherals are enabled, which makes up for 3 use cases (both on and 2 more with either on). Some pins stay afloat when they’re not being used, which causes occasional readings of the floating signals to show on the Data section of the analyzer, and I assume that implies in more unnecessary strain on the analyzer? Idk. Sure, I could disable the streaming of the unused analyzer, etc, or there could be a single toggle button that solves does away with it all.

As for the channel resizing thing, you really nailed it on v. 1.2.29. I guess it’s because everything seems bigger on Logic 2? Anyway, I’m just making a case for equally sized channels, with a bias towards it being smaller.

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Thanks for helping me to understand your use case and your preference for things being consistently sized and compact.

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I am playing again with OV7670 camera on with a different wiring (using 2nd camera and Teensy 4.1)
So have all 16 signals hooked up to my old Logic 16. I did not hook up the logic pins to same wires as last time instead I hooked them up more or less in camera pin order. As such my Simple Parallel did not use pins 0-7 for data, but instead 6-13, but when it displays it is not putting all of the “dots” in the right places i.e. it is still putting some of them in 0-3 pin lines…

Which hopefully this image shows up well enough

Thanks Kurt, I was able to reproduce it. Very odd. The same bug does not appear to apply to other analyzers like async serial. Looking into it.

Ok, found the problem, it was a small bug in the parallel analyzer, which should have only affected which channels the markers were added to. I’ve fixed the bug, but since we’re in the middle of releasing 2.3.12 right now, the fix might get pushed to the next release. Thanks for reporting this!

Glad you found it… If it makes in the next build great if the one after, not that big of a deal. I did find the issue I was looking for, and I can always rearrange all 16 connections

Thanks for reporting this we released 2.3.12 with the fix. Let us know if you have any questions.

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Thanks again, looks like it is working

@jberkhout @P.Jaquiery I just added a new idea and your notes below: