Well, it does work. You just tap the CAN-LO pin and the system ground and it should work fine in the digital domain. Plenty of us do it. But, I do wish there were more options - for instance my idea to allow for “digitizing” an analog capture to turn an oscilloscope capture into digital input to something like the CAN-FD decoder. Then you could define custom thresholds. Alas, this is not yet possible. But, in the meantime things do normally work in the digital domain as long as you pretend CAN-HI doesn’t exist.
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Interesting. For me, it doesn’t. The digital always stays high. Please review the attached screenshots. I have connected D8 to CAN_L of a WaveShare Isolated CAN-FD HAT – and the corresponding ground to its GND.
Did you try changing the voltage setpoint? It seems to me that I’d usually use 3.3+v mode as I think that 2.5 or 1.8v mode is going to be such that you can never drop low enough to trigger as being a “low” signal. From your oscilloscope traces I can see that CAN-L floats up around perhaps 2.8 - 2.9v relative to your system ground. That could also be the problem. Usually the recessive voltage is around 2.4 - 2.5v and that makes the dominant bits be lower voltage too. It’s possible your bus is running just slightly too high for the Logic to pick up the low bits. In that case, that’s a real bummer.
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I’m at 3.3+v mode because I want to measure SPI in parallel. Is it safe to move to a lower voltage mode and then “overshoot” the SPI inputs?
It’s always safe to use any threshold setting, this just changes the input voltage to the comparators at the input of the device.
Using a lower threshold than necessary can increase the amount of noise picked up by the digital recording. The software has an optional “glitch filter” which you can use to try and compensate for this.
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According to: Supported Voltages - Saleae Support
You can see the analog voltage levels for various versions of Logic hardware to detect a digital ‘1’ vs. ‘0’ on the CAN bus.
Meanwhile, as per: CAN bus - Wikipedia
the CAN bus is nominally biased at +2.5V (idle, passive logic ‘1’ state) and CANH is driven up to +3.5V while CANL is driven down to +1.5V in the active (logic ‘0’) state.
In your capture, it looks like your CAN bus is at a higher offset voltage (>2.5V), such that CANL channel may not be crossing the digital threshold voltage to see a ‘0’ vs. ‘1’ on the bus.
This could be related to:
- ground/offset (make sure you tie analyzer to GND with minimal impedance)
- poor bus loading (make sure bus is terminated with proper resistance between CANH/L – nominally 60 ohms via two 120 ohm terminating resistors)
- other physical layer/electrical issues (try to capture close to transmitting node, minimize sources of interference, and confirm good contact/connections to bus)
The actual ‘1’ vs. ‘0’ is a differential voltage (i.e., CANH - CANL) and >0.5V minimum required, I think (but should be ~1-2V typically). A CAN transceiver will translate this differential bus voltage to a nice digital input voltage (i.e., 0V to 3.3V/5.0V depending on VDD of I/O pins on an ‘RX’ pin) that is easier to probe with digital logic analyzer. Otherwise, you could buy a high speed differential probe, but for CAN bus you would be better off just using a separate CAN transceiver board if you can’t probe the ‘RX’ pin directly. Just make sure to also connect the transceiver board to a common ground and provide a suitable VDD reference voltage.
Note: I have successfully probed CANL directly on a ‘good’ bus (2.5V bias, etc.) but prefer to probe ‘RX’ instead, when available.
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Thanks all for your comments.
Turned out I had a misconfigured CAN transceiver that was expecting 3.3V instead of (the supplied) 5V. This lead to the CAN levels being out-of-bounds. Not a problem for the actual CAN bus (due to its differential nature), but just a tad bit too high for the logic analyzer.
Guess what… if you do it correctly, it works. I’m very happy now, thanks again! And by the way… happy new year!
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