hello there, planning to buy/use saleae as a logic analyze, but I need a special SPI feature. It’s for SPI-DDR. 3-wire SPI with double data rate, clock on both rise and falling edge. would it be easy to implement?
@fgravel Thanks for writing in! I replied to your email last week. I’ll post my reply here for visibility.
In short, our pre-installed SPI analyzer currently does not have the capability of decoding bits on both rising edges and falling edges. You can only select one type of edge.
As such, a custom C++ low level analyzer utilizing our Protocol Analyzer SDK may be the best solution. Using this SDK, you’d be able to modify our pre-installed SPI analyzer to add that capability. Our SPI analyzer source code can be found below for quick reference.
Although we don’t offer services for developing custom analyzers, I did want to shout out the folks over at Binho! Their engineers are able to provide services to develop custom low level analyzers and extensions for our software. More information on their services can be found in the link below in case you are interested in reaching out to them.
Feel free to let me know if you have any questions!
Thank you Tim
Thanks for sharing the code
I’m working on it right now, modifying the SDK. Thanks to ChatGPT for helping me to modify it 
I’m waiting for the pod I ordered to arrive. I’m working with the demo mode for the moment.
I succeeded to double the clock. I’m working on the SpiAnalyzerResults.cpp right now to generate the proper table result in csv.
Thanks again
Felix
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