Simple Parallel Analyzer does not trigger properly

Here’s an image of a capture performed on digital signals using the Simple Parallel protocol to combine 3 address lines into a hex value using a fourth line as the clock and triggering on the rising edge. As is easily seen, what it is calling a rising edge isn’t. Is there a simple way to fix this?

yup. I posted this in github before coming here.

@emaynard Thanks for confirming that was you.

As a first step, I’d like to grab your capture file (in .sal file format). Can you upload that here?

@emaynard Sounds good. We’ll leave this forum post open. Feel free to post back here if you have any updates. It certainly does sound like some kind of corner case.

I got one! Here’s a capture that shows bad triggering.

I hid all channels but cal mux a0, cal mux a1, cal mux a2, demux a0, demux a1, demux a2, demux en

Created a simple parallel analyzer with cal mux a0, cal mux aq, cal mux a2 and the clock as demux en set to rising.

Turned off the alternate outputs (table, etc)

The program is marking the rising edge transitions on the falling edge.

Let me know if you can recreate the issue.

Ed

calmux 100 bad triggering.sal (43.9 KB)

Additional information: Looks like dual edge captures the rising and falling edges correctly.

Can we skip the advertising?

Removed the large automatically attached graphic that was placed by hitting “Reply” in the email.

So, yes, I suppose we can skip the advertising.

@emaynard Ah, I see it now, you’re right! We seem to have broken something when we implemented dual edge support :man_facepalming:

Thanks for providing that capture file. It seems I can reproduce this with simulation captures as well. This should be fairly straightforward to fix. I’ll keep you updated.

@emaynard We’ve got a fix planned for the next release (v2.4.7).