Having trouble decoding RS485 modbus captured using the analyzer. We are reading 16 registers from device 01, writing 2 registers to device 01, reading 16 registers from device 05, and then writing 2 registers to device 05 in a continous loop. I stop the trace after an error is detected.
I have other programs actively reading and responding to the line so I know it’s electrically sound at least until the error, and I feel like I should be able to parse with the logic analyzer.
Baud is 38400 with even parity.
Sometimes the data looks right to an extent
@r.henderson.cheeng Sorry for the trouble with that! Based on the images you shared, I notice a few glitches in your waveform that might be throwing off the Modbus analyzer. This is especially apparent in your second image.
Can you try using our software glitch filter to eliminate those glitches to see if that solve it for you? Instructions are provided below:
@timreyes I can definitely try that. Is it possible to try different values on the same capture or do you have to recapture? Any suggestions on a time basis for the filter to try? Below is a capture of the traffic over the serial port and the capture via the Logic software. Seems to be going ok and then falls apart in the middle.
@r.henderson.cheeng Ah sorry for not mentioning the limitation of our glitch filter! Unfortunately, glitch filters are a pre-process and not a post-process, meaning it must be applied before a capture and cannot be applied after the capture has completed. I understand it’s a pain having to re-take the capture. Sorry about that. We’re tracking the feature request below in case you’re interested in voting for it:
After looking at your capture, I notice that the glitch pulses are in the ballpark of being ~500 ns long. On the other hand, a single valid bit is about 26us long. Therefore, I think setting your glitch filter to 2us should be safe to filter glitches less than 2us, and wouldn’t affect your valid data. If you still notice glitches afterwards, you can bump up the glitch filter even further since you still have room to work with given that valid data bits are 26us long.
Another thing I notice is there’s a drop in voltage amplitude, likely due to a difference between trasmit and response amplitudes. See image below:
You’ll need to ensure that your data meets the voltage threshold specification of Logic 8 mentioned below in order for the logic LOWs and logic HIGHs to be effectively recorded. The smaller voltage amplitude signal to the right doesn’t seem to be crossing that threshold, hence the tiny glitches seen in the capture, likely due to ringing at the edges.