I normally use a Logic 8 Pro, but we also have a Logic 4 that I thought I’d carry around with me.
Set a post trigger capture time of 10 seconds at 12.5Ms/s, capture a 1MHz signal
Results: After trig, capture runs for 10s
- The trace displayed is 5s length
- 1MHz signal displays as 2MHz.
- Times between edges are 1/2 of what they should be.
Maybe something to do with 4 bits per sample instead of 8 bits?
Happy to test if you find this not reproducible.
@jeff1 Whoa… thanks for letting us know about this. Could you send us a copy of your capture file that shows this issue?
Hi Tim, thanks for looking into this.
Here are 2 captures, just simple read of ID from an SPI FLASH.
- The clock is 1MHz (when running)
- Trigger is /cs channel 2
- Pre-trig trim is on, set to 1ms
- Capture duration post trig 1s
The 6MHz sample rate capture looks correct, showing 1MHz clock.
The 12MHz capture doesn’t, showing 2MHz clock, and is short of the 1s post trigger time.
The signals are of course different runs, but the same hardware so are the same frequency.
I would suspect USB overrun or something, but that doesn’t explain why the clock frequency changes.
Logic 2.4.10 Linux x64
Cap_1MHz_1s_6Msa_s.sal (4.2 KB)
Cap_1MHz_1s_12Msa_s.sal (3.4 KB)
Hi Tim, thanks again for looking into this.
With a Logic 4 device, and Logic 2.4.11 software, on an Linux x64 host,
Using the same test signals as above (an SPI transfer with 1MHz clock),
The same incorrect capture is consistently produced at 12Ms/s.
- Short post trigger capture time (very early termination, actually)
- Edges are reported 1/2 of the actual time apart (that is, clock appears are 2MHz)
6Ms/s and below appear to work correctly, tested at 6Ms/s and 3Ms/s, with both capturing the 1MHz clock (as) correctly (as possible with a 3MHz sample rate).
The above captures from Logic 2.4.10 are still indicative of this behavior. Here are new screenshots from 2.4.11
How can I help debug?
@jeff1 We looked into this some more, and we weren’t able to reproduce the behavior on Ubuntu 22.04 (recording a 1MHz clock).
I’ve provided our capture file results below for reference. Both sampling rate settings were tested on a 1MHz clock.
TR-1MHz-6MSa.sal (6.8 KB)
TR-1MHz-12Msa.sal (6.1 KB)
I’m not quite sure how the issue is manifesting on your end. It’s not immediately apparent from your capture files, though all of your edges being reported as 1/2 of the actual time is quite apparent.
I have some follow up questions for you:
- What Linux Distro are you using?
- Can you try connecting CH0 to the 1 MHz clock signal, and record it at 12MS/s, including Analog CH0? Can you send the resulting capture file over? I’m wondering if including the analog signal representation of the 1MHz clock might provide us with some more clues to work with.
- Are you able to test this behavior on another PC with an operating system that we officially support? I’d like to see if the issue might be specific to your Linux distro, though it’s unlikely.
Without any leads, we may consider sending you a replacement Logic 4 device to test out. We can open up a private email chain in case we take this route, as we’d like to gather your device and shipping address information.