Look for any ‘glitches’ in the waveform
(i.e., any pulse widths less than minimum expected widths listed below)
Consider re-capturing using a software glitch filter to filter out any such glitches
(or improve hardware connections/signal quality to eliminate such glitches)
Confirm the sync pattern is seen at the start of packets:
(i.e., KJKJKJKK pattern, or 0b00000001)
Confirm the bitstream bit widths (pulse widths) are consistent with the expected bit rates, especially during ‘sync’ /start of packet:
Low Speed/LS (1.5 Mbps): no faster than 1/1.5 MHz or ~667 ns
Full Speed/FS (12 Mbps): no faster than 1/12 MHz or ~83.3 ns
Confirm the end-of-packet (EOP) at end of packets:
2 x SE0 (D+/D- both LOW) + ‘J’ (D+ high, D- low) before bus is ‘idle’
Confirm USB LS and FS Analyzer Settings
Confirm D+ and D- Channels are mapped correctly
Confirm USB bit-rate is set as expected
(i.e., LS/1.5 Mbps vs. FS/12 Mbps)
Confirm USB decode level settings
Consider using lower-level Bytes or Signals to confirm basic decoding
Use Packets or Control transfers for a higher level USB decoding view
Verify the voltage levels on the D+/D- signals
(enable analog capture in the device capture settings)
Note: the Saleae Logic officially has only 1 MHz analog bandwidth (10 MS/s sample rate) or 5 MHz analog bandwidth (50 MS/s sample rate), depending on ‘regular’ vs. ‘pro’ model, so may need at least ~[200 - 1000] ns pulse width in the same logic ‘high’ state to actually ‘see’ the full ~3.3V level on D+/D- pin
(capture analog w/ maximum sample rate supported: 50 MS/s or 10 MS/s)
You Might need to use a higher bandwidth ‘real’ analog scope to more easily confirm the real voltage levels while USB is ‘running’
(however, should at least have enough ‘idle’ time intervals to confirm D+ voltage range is ~3V (LS/FS speeds), not always < 1V (USB 2.0+ speeds))