Saleae

Discrepancies between analog and digital readings

I’m using Logic 8 with software 1.2.18 on Linux . Sometimes, I see different results for analog and digital representations of the same channel. Here’s an example. The pulses appear of equal length in Analog, but the high pulses are longer than low in digital. Same channel.

Another issue that’s been coming up is a kind of glitch, or a piece of noise. This screenshot is a zoom into the same capture as above. The analog is smooth at 0V, but the digital shows a 10ns (one-sample) dip.

I assume that analog is the more accurate in this case, mostly because it shows what I want to see :=) Seriously, though, looking at the capture, I can’t tell if my DUT is generating correct signals and Logic displays them funny, or if the DUT is glitching.

Ari.


It looks the same in 2.0.7

Hi Ari,

Sorry about this, and thanks for posting! I suspect there are two things at play.

  1. Our Logic 8’s voltage threshold is fixed at the following levels
  • Voltage input LOW: 0.6 volts
  • Voltage input HIGH: 1.2 volts
    Regarding your first image, it looks like it takes some time before the digital channel will recognize it as a LOW signal. At what analog voltage reading does the digital transition from HIGH to LOW?
  1. For your second image, although the digital channels have an adequate sampling rate to capture the glitches, the analog channel’s sampling rate is unfortunately unable to keep up. Each dot in the analog capture represents the sample points, and the line that is drawn between them is a mathematical interpolation. In addition, the digital and analog on a single channel take different paths internally in the hardware.

More information here: https://support.saleae.com/troubleshooting/digital-and-analog-appear-different

Our eventual goal is to support higher bandwidths in the next generation hardware.

You could always throw it on a scope. I have done that a bit to verify signals that the Saleae device has captures, especially the analog signals since it does sometimes lag/struggle to keep up.

Here’s what I’m taking away from this conversation and others offline.

  1. Our low-level signal is above 0V, as a result of a board layout quirk.
  2. This messes up Logic’s notion of high-to-low and low-to-high transitions, so that 50% duty cycle appears to have shorter positive than negative pulses.
  3. The one-sample glitch is hysteresis. It will probably go away if the signal goes all the way to ground instead of flattening out at the positive offset.

Thank you to Tim, Mark, Jonathan and others who helped decipher these observations.