# Demodulation signal using 1-Wire **URL:** \ **Category:** Support\ **Created:** [April 15, 2025, 2:34pm UTC](https://discuss.saleae.com/t/demodulation-signal-using-1-wire/3353 "2025-04-15T14:34:20Z")\ **Posts on this page:** 7\ **Page:** 1
**Author:** ![jackson.santos.veiga](https://avatars.discourse-cdn.com/v4/letter/j/9de053/32.png) [@jackson.santos.veiga](https://discuss.saleae.com/u/jackson.santos.veiga)\ **Post date:** [April 15, 2025, 2:34pm UTC](https://discuss.saleae.com/t/demodulation-signal-using-1-wire/3353/1 "2025-04-15T14:34:20Z")
Hello everyone, I’m trying to decode the 1-Wire signal using Saleae (Logic 2 Version 2.4.22) It doesn’t recognize the data, as shown in the image below: ![image](https://canada1.discourse-cdn.com/flex030/uploads/saleae/original/2X/c/cab7d9904d84cffa5d973b000e2c25af4a48730c.png) Can anyone help me? ---
**Author:** ![BitBob](https://yyz2.discourse-cdn.com/flex030/user_avatar/discuss.saleae.com/bitbob/32/2292_2.png) [@BitBob](https://discuss.saleae.com/u/BitBob)\ **Post date:** [April 16, 2025, 1:11am UTC](https://discuss.saleae.com/t/demodulation-signal-using-1-wire/3353/2 "2025-04-16T01:11:13Z")
Do you have a `*.sal` capture file you could share? Hard to check signal timing from the screenshot alone. ---
**Author:** ![jackson.santos.veiga](https://avatars.discourse-cdn.com/v4/letter/j/9de053/32.png) [@jackson.santos.veiga](https://discuss.saleae.com/u/jackson.santos.veiga)\ **Post date:** [April 16, 2025, 2:02pm UTC](https://discuss.saleae.com/t/demodulation-signal-using-1-wire/3353/3 "2025-04-16T14:02:46Z")
Yes, I have. [KIT.sal](https://discuss.saleae.com/uploads/short-url/yskH4LKnVGvnUiELf9phqWx9UCg.sal) (503.8 KB) ![image](https://canada1.discourse-cdn.com/flex030/uploads/saleae/original/2X/a/aca558e74c021cfe047be22c1bd614f23e020cda.png) S: Start Bit P Parity Bit The conditioner responds ACK ![image](https://canada1.discourse-cdn.com/flex030/uploads/saleae/original/2X/b/bc94fccb587a2715a9033a1970f97bd05337288e.png) S: Start Bit P: Parity Bit ![image](https://canada1.discourse-cdn.com/flex030/uploads/saleae/original/2X/c/c79fc8276e01538e8572123f728714ab7f35bf95.png) ![image](https://canada1.discourse-cdn.com/flex030/uploads/saleae/original/2X/c/c6783b3ad702ad65c0358d130237adacd5dc5fd9.png) ---
**Author:** ![BitBob](https://yyz2.discourse-cdn.com/flex030/user_avatar/discuss.saleae.com/bitbob/32/2292_2.png) [@BitBob](https://discuss.saleae.com/u/BitBob)\ **Post date:** [April 17, 2025, 12:46am UTC](https://discuss.saleae.com/t/demodulation-signal-using-1-wire/3353/4 "2025-04-17T00:46:15Z")
What device or protocol is that? I’m pretty sure 1-Wire is defined as per this: > **[1-Wire](https://en.m.wikipedia.org/wiki/1-Wire)** > > 1-Wire is a wired half-duplex serial bus designed by Dallas Semiconductor that provides low-speed (16.3 kbit/s) data communication and supply voltage over a single conductor. > 1-Wire is similar in concept to I2C, but with lower data rates and longer range. It is typically used to communicate with small inexpensive devices such as digital thermometers and weather instruments. A network of 1-Wire devices with an associated master device is called a MicroLAN. The protocol is also used in small elect... …which has a different bit encoding than your pictures. See also: [https://www.analog.com/en/resources/app-notes/reading-and-writing-1wirereg-devices-through-serial-interfaces.html](https://www.analog.com/en/resources/app-notes/reading-and-writing-1wirereg-devices-through-serial-interfaces.html) Knowing the device / datasheet may help identify a different analyzer vs. “1-Wire” you are using. ---
**Author:** ![jackson.santos.veiga](https://avatars.discourse-cdn.com/v4/letter/j/9de053/32.png) [@jackson.santos.veiga](https://discuss.saleae.com/u/jackson.santos.veiga)\ **Post date:** [April 17, 2025, 10:56am UTC](https://discuss.saleae.com/t/demodulation-signal-using-1-wire/3353/5 "2025-04-17T10:56:26Z")
Thank you very much for your help. I am basing this datasheet on my work. [IDT\_ZSC31010\_DST\_20160120\_1.pdf](https://discuss.saleae.com/uploads/short-url/xxv2bdKBk2NLnr9bWsKeR5YRyGU.pdf) (568.4 KB) ---
**Author:** ![BitBob](https://yyz2.discourse-cdn.com/flex030/user_avatar/discuss.saleae.com/bitbob/32/2292_2.png) [@BitBob](https://discuss.saleae.com/u/BitBob)\ **Post date:** [April 18, 2025, 11:54am UTC](https://discuss.saleae.com/t/demodulation-signal-using-1-wire/3353/6 "2025-04-18T11:54:30Z")
That datasheet helps to identify the protocol, and while they call it “one wire interface” (OWI), it is not the same as 1-Wire described at links above – it is also called “ZACwire™”, and is a PWM encoded scheme. I think you’d need to use the [Saleae Analyzer SDK](https://support.saleae.com/saleae-api-and-sdk/protocol-analyzer-sdk) to make a custom protocol decoder, as I am not aware of an existing one to use. I did find an [old blog post about ZACwire analysis](https://nitschinger.at/Digging-into-TSIC-and-ZACWire-with-the-Saleae-Logic-Analyzer/), but the author apparently never followed through with the custom analyzer for Saleae used to study the protocol. Looking a little deeper into the bit-level encoding, you _might_ be able to hack a quick decoder with the [async serial analyzer](https://support.saleae.com/protocol-analyzers/analyzer-user-guides/using-async-serial), by using non-standard 6N1 decoding and the right bit rate. That is doing: - 1 start bit (always low) - 6 data bits - 1 stop bit (always high) The bit patterns would be: - 00001111 = strobe (50%) - 00111111 = ‘1’ (75%) - 00000011 = ‘0’ (25%) Convert/display as hex vs. binary, and don’t forget it’ll be little-endian (least significant bit first) by default, and the 6 middle bits are the data bits while first 0 is a ‘start’ bit and last 1 is a ‘stop’ bit. Thus, you would get a ‘byte’ of 6N1 data per ‘bit’ of ZACwire protocol, and you would need to combine & decode/map those ‘byte’ values back to the logical 1’s and 0’s from above. Maybe not so helpful afterall, but just a thought 🥴 Otherwise, if C++ isn’t your preferred language, you can use the [high-level analyzer (HLA) python API](https://support.saleae.com/extensions/high-level-analyzer-extensions) to develop something, too. Either chain it to the async analyzer mentioned above, or do something from scratch … possibly linked to the [Saleae simple parallel analyzer](https://support.saleae.com/protocol-analyzers/analyzer-user-guides/using-simple-parallel) instead. Just set the D0 and Clock both to your one wire channel, and the Clock State to BOTH edges. Then you get a 0 or 1 + timestamp at each falling/rising edge to build up your custom decoder in python. ---
**Author:** ![jackson.santos.veiga](https://avatars.discourse-cdn.com/v4/letter/j/9de053/32.png) [@jackson.santos.veiga](https://discuss.saleae.com/u/jackson.santos.veiga)\ **Post date:** [April 23, 2025, 4:40pm UTC](https://discuss.saleae.com/t/demodulation-signal-using-1-wire/3353/7 "2025-04-23T16:40:51Z")
Thanks for the help BitBob. I’ll give this a try. 🙂